1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device and, in particular, to the manufacturing of a wire structure.
2. Description of the Related Art
In recent years, copper that has a lower resistance than that of aluminum has come to be used as a wire material in semiconductor integrated circuits. The Damascene method is used in the manufacturing of a semiconductor device wherein wire trenches are formed in an interlayer insulating film using a dry etching technique, and the wire material is filled into these wire trenches.
In the following, a conventional manufacturing method of a wire will be described with reference to FIGS. 5A to 5F.
FIGS. 5A to 5F are cross sectional views showing a conventional manufacturing processes in sequence of a semiconductor device that uses a copper wire, wherein FIG. 5A is a cross sectional view showing a conventional process of forming a via hole resist pattern, FIG. 5B is a cross sectional view showing a conventional process of forming a via hole, FIG. 5C is a cross sectional view showing a conventional process of removing the resist pattern, FIG. 5D is a cross sectional view showing a conventional process of forming an opening in an insulating film, FIG. 5E is a cross sectional view showing a conventional process of cleaning the bottom of the via hole, and FIG. 5F is a cross sectional view showing a conventional process of forming a metal plug.
First, in the process of forming the resist pattern shown in FIG. 5A, a copper wire 73 is formed above a semiconductor substrate 71 made of silicon, in such a manner that the side surfaces and the bottom surface of the copper wire 73 are covered with an insulating film 72 made of silicon oxide. Subsequently, an insulating film 74 made of silicon nitride is formed on top of the insulating film 72 and the copper wire 73. An insulating film 75 made of silicon oxide is formed on the insulating film 74, and thereafter a resist pattern 76 with an opening 77 is formed.
Next, in the process of forming a via hole shown in FIG. 5B, etching is carried out on the insulating film 75 using the resist pattern 76 as a mask by the plasma dry etching method, so that a via hole 77a is formed.
Next, in the ashing process shown in FIG. 5C, the resist pattern 76 is removed and, after that, in the process of exposing the metal wire shown in FIG. 5D, the entire surface of the semiconductor device is etched back by the plasma dry etching method, so that a via hole 77b is formed so as to expose the copper wire 73 from the insulating film 74. In this process, for example, a parallel plate type RIE unit is used wherein the flow rate of CF4 which is an etching gas is set at 50 sccm, the flow rate of O2 which is a control gas for the etching deposit is set at 10 sccm, the temperature of the substrate is set at 25° C., the RF output is set at 300 W and the pressure is set at 5 Pa. At this time, O2 is used for controlling the deposit which is an etching reaction product; therefore, the surface of the base copper wire 73 is oxidized, so that a copper oxide layer 78 is formed.
Finally, as shown in FIG. 5E, the semiconductor device is cleaned with a chemical having an etching selectivity of copper oxide to copper that is almost infinite in a typical cleaning manner using a chemical that includes an organic acid such as ammonium fluoride or ammonium acetate, so that the copper oxide layer 78 is removed. After that, as shown in FIG. 5F, a metal plug 79, also made of copper, is formed as a portion of the upper layer wire that includes the portions making contact with the bottom and walls of the via hole 77b. 